The present invention relates to a semiconductor integrated circuit device having a functional circuit block (such as a memory, an arithmetic and logic unit or an I/O controller) for which low power consumption is desired, such as a built-in cache memory for which high speed accessing and multi-bit output are required, and to a microprocessor.
In a recent high speed microprocessor (MPU), it is common to build in a cache memory in the MPU and enhance a parallel operation to improve a processing capability in order to solve a problem caused by the inconsistency of an internal instruction execution speed and a transfer speed of an instruction and an operand from an external main memory. As a result, the increase of power consumption has become a serious problem.
A primary purpose of building in the cache memory is to fetch an instruction or data at a high speed consistent with an execution speed of the MPU.
A clock period of a complex instruction set computer (CISC) type MPU which is of a highest speed as of today is 25-40 MHz. It is expected that in a near future a reduced instruction set computer (RISC) type MPU which is over 100 MHz will come up.
In such an ultra high speed MPU, an ultra high accessing speed of less than several ns is required for the built-in cache memory.
The built-in cache memory has a feature of a relatively small number of words and an extremely large number of readout bits per word (8 bits at maximum in a general purpose SRAM). For example, in a today 32-bit MPU, the parallel readout of several hundreds bits is common, and the number of parallel readout bits will further increase if a 64-bit MPU is introduced in future.
In general, a differential type high sensitivity sense amplifier which uses bipolar transistors is suitable for a sense amplifier of the ultra high speed memory. However, this circuit constantly consumes a relatively large power. Further, a power is consumed by other portion of the memory even if the memory is not accessed unless special power consumption saving means is provided.
Thus, in a single chip MPU which builds in an ultra high accessing speed and multi-bit parallel output cache memory, the power consumption by the memory circuit is extremely large and an on-chip cache memory would ultimately be not attained unless appropriate power consumption saving means is provided.
In first prior art technique known as power consumption saving technique, the memory circuit is switched between a power consumption in a stand-by mode and a power consumption in a normal operation mode by a chip select signal CS which is equivalent to a memory address signal in order to reduce an effective power consumption.
In another prior art technique, a change in an address signal is detected by an address transition detector (ATD) circuit, a clock pulse required for an internal operation is generated in response to the detection signal, and a sense amplifier of a memory is activated only for a required period to reduce the power consumption.
Further, as shown in JP-A-61-45354, in a logic LSI such as an MPU, a) a method of providing power control instructions one for each of a plurality of functional blocks and selectively activating and deactivating corresponding functional blocks by a program to reduce the power consumption, b) a method for providing a clock control circuit for each functional block and controlling the supply or the non-supply of a clock is controlled to reduce the power consumption, and c) a method of providing a power control circuit for each functional block and stopping the supply of a power to the functional block which is not used in the execution of an instruction to reduce the power consumption, have been known. However, in the prior art, consideration is not paid to noises induced in a power line and a ground line by a sudden change in a power supply current during the switching between the normal power consumption mode and the low power consumption mode. Thus, it includes the following problems. 1) Since the circuit current significantly changes in a short time between the low power consumption mode and the normal operation mode, a large noise voltage is induced by inductances and resistances of the power line and the ground line. 2) The functional circuit itself or other internal circuit malfunctions due to the noise voltage. Even if it does not malfunction, a certain time period is required to extinguish the noise voltage and an effective memory accessing speed is lowered.
FIG. 24(a) illustrates the development of the noise voltage of the power supply line. Numeral 1300 denotes a power supply, numeral 1310 denotes a functional circuit block such as a memory circuit, numerals 1321 and 1322 denote inductances of the power supply line and a ground system, respectively, and numerals 1331 and 1332 denote resistances of the power supply line and the ground system, respectively.
FIG. 24(B) shows a change in a power supply current i and changes in a power supply voltage v.sub.1 and a ground potential v.sub.2 when a switch SW is turned on at a time t.sub.1 and turned off at a time t.sub.2.
As shown, when the switch SW is turned on at the time t.sub.1, the circuit current i changes from zero to a steady state current in a time period .DELTA.t.sub.1. The power supply voltage v.sub.1 of the circuit largely changes to exhibit a peak in a negative direction, and the ground potential largely change t.sub.o exhibit a peak in a positive direction. On the other hand, when the switch SW is turned off at the time t.sub.2, the circuit current i changes from the steady state current to zero in a time period .DELTA.t.sub.2. The power supply voltage v.sub.1 of the circuit largely changes to exhibit a peak in the positive direction, and the ground potential v.sub.2 largely changes to exhibit a peak in the negative direction.
It is assumed that the circuit 1310 of FIG. 24 comprises 500 sense amplifiers which consume current of 2 mA per circuit and the current is switched from zero to the steady state current in .DELTA.t=1 ns. Assuming that the resistances 1331 and 1332 are neglected and the inductances 1321 and 1322 are L=5 nH, the power supply noise v.sub.n is given by ##EQU1## Such a large power supply noise is not permitted in the today's semiconductor integrated circuit which operates at a power supply voltage of 5 volts or lower.
Even if the noise can be reduced to an appropriate level, the times t.sub.1 and t.sub.2 are required to extinguish the power supply noise and the ground noise, as shown in FIG. 24(B). This time depends on the current switching time and it is normally 103 ns. This time is not acceptable by the ultra high speed memory which requires the access time of less than several ns, and it is a great obstacle to the high speed operation.
The problem caused by the change in the power supply current is equally applicable to a plurality of arithmetic and logic units in a semiconductor chip and other functional circuit block.
In a recent high performance MPU, various techniques have been introduced in order to enhance its processing performance. The processing performance of the computer is evaluated by: ##EQU2## where CPI is the number of cycles required for one instruction.
A noticeable technology in those several years is a RISC processor. In the RISC, it is a primary goal to proximate the CPI to one in order to enhance the performance.
Recently, a super scalar and a VLIW (very long instruction word) have been noticed as the next technology to the RISC. In this technology, up to n instructions are parallelly read, the n instructions are parallelly decoded and the n instructions are parallelly executed. By increasing the parallelism of the hardware, the CPI in the above formula is reduced to 1/n in order to enhance the performance of the computer. In the high speed arithmetic and logic circuit of the super scalar or the VLIW, a differential logic circuit by bipolar transistors or a low amplitude circuit by BiCMOS is used, but a circuit which draws a DC current steadily consumes a relatively high power.
In the super scalar or VLIW MPU, n high speed arithmetic and logic circuits of the same function are required. As a result, the power consumption of the arithmetic and logic circuits increases by the factor of n.
A related technology is discussed in NIKKEI Electronics, No. 487 Nov. 27, 1989, pages 191-200.
As seen from the above description, in the prior art power consumption saving technique in the semiconductor integrated circuit or electronic circuit such as a microprocessor, the problem of noise developed on the ground line or the power supply line when the power is switched is not taken into account and hence the circuit malfunctions or a certain time is required before the noise disappears, and a rapid start-up is not attained.
In the prior art MPU having the on-chip memory, because of trade-off between the noise reduction in the power switching and the speed-up of the memory accessing, it is difficult to attain very high operating speed.
While the microprocessor having a cache memory has been discussed above, the same problem is encountered in a semiconductor integrated circuit or an electronic circuit having a functional block which requires a high speed operation.